The invention relates to a semiconductor device comprising a non-volatile storage transistor having a charge storage region which comprises an insulated conductive layer, and a control electrode coupled capacitively to the insulated conductive layer, while charge stored in the charge storage region represents information and the storage transistor for reading the information is included in a main current path of the storage cell, comprising a semiconductor body with a semiconductor surfeace at which are located a first and a second electrode region and a channel region of the storage transistor, which form part of the main current path, the semiconductor surface locally adjoining a first thick insulating layer which, viewed on the semiconductor surface, is bounded by a first edge, the first and the second electrode region each forming a rectifying junction with an adjoining common substrate region of a first conductivity type and the channel region being separated by a second thin insulating layer from a first part of the insulated conductive layer, wherein at the semiconductor surface there is disposed an injector region of a second conductivity type opposite to the first conductivity type which adjoins the common substrate region and which, viewed on the semiconductor surface, is entirely on losed by the first thick insulating layer and is separated by a third thin insulating layer from a second part of the insulated conductive layer, the first and the second part of the insulated conductive layer being interconnected by a third part separated by the first thick insulating layer from the semiconductor surface, while a semiconductor zone of the second conductivity type covered by the first thick insulating layer and forming an electrical connection for the injector region forms part of the second electrode region.
Such a semiconductor device is known from European Patent Application No. 86372 published on Aug. 24, 1983. This Patent Application discloses a non-volatile storage transistor having a floating gate, in which the injector region, viewed on the surface, is entirely enclosed by the first thick insulating layer obtained by local oxidation of the semiconductor body. On this enclosed injector region is disposed a thin tunnel oxide. By the use of local oxidation, in the case an enclosed tunnel region having a comparatively small surface area can be obtained by means of a photolithographically formed and oxidation-resistant mask still having comparatively large dimensions because after oxidation the non-oxidized part of the semiconductor surface is automatically smaller than the provided mask due to growth under this mask.
Generally, a comparatively high programming voltage is required for programming non-volatile storage transistors. This voltage is higher than the voltage s which are usual in conventional integrated circuits without non-volatile storage transistors. Frequently, non-volatile storages are therefore manufactured by means of a particular technology adapted to the high programming voltage. It is then of importance inter alia that the breakdown voltage of the pn junctions and the parasitic threshold voltage in that part of the semiconductor device which is covered by a comparatively thick field oxide are sufficiently high so that the programming voltage in the semiconductor device does not produce breakdown and does not lead to parasitic channel formation.
The choice of the value of the programming voltage depends upon the desired programming time and the desired hold time. The hold time is determined to a considerable extent by the thickness and the quality of the third thin insulating layer present on the injector region. The programming time is further dependent to a considerable extent upon the chosen third thin insulating layer and upon the value of the voltage difference which is available during programming between the injector region and the insulated conductive layer. This voltage difference is a part of the programming voltage practically determined by the ratio between the capacitance of the insulated conductive layer with respect to the control electrode and the overall capacitance of the insulated conductive layer. This overall capacitance comprises, besides the capacitance with respect to the control electrode, also the capacitance with respect to the control electrode zone and the injector region, the capacitance with respect to the substrate region and the capacitance with respect to the first electrode zone. The said capacitance ratio is designated as the coupling factor.
The known storage transistor described above has, as stated, the advantage that the tunnel region is comparatively small. However, a disadvantage is inter alia that in this storage transistor the second electrode zone has joined to it a comparatively large doped subzone which is situated under the first thick insulating layer. This additional subzone has to be comparatively large in order to ensure that the third thin insulating layer is continuously located above this subzone and moreover the tunnel region is continuously connected to the part of the second electrode zone not covered by the thick insulating layer, also if the masks used in the manufacture, which are important in this respect, are not ideally aligned.